5 output enable, 6 syncmanager watchdog, Output enable – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual

5 output enable, 6 syncmanager watchdog, Output enable | Syncmanager watchdog, Figure 38: digital output principle schematic | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual | Page 106 / 144