7 sof, 8 outvalid, 9 timing specifications – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual

7 sof, 8 outvalid, 9 timing specifications | Outvalid, Timing specifications | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual | Page 107 / 144