6 tested fpga/designflow combinations, Tested fpga/designflow combinations, Table 3: tested fpga/designflow combinations – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual

6 tested fpga/designflow combinations, Tested fpga/designflow combinations, Table 3: tested fpga/designflow combinations | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual | Page 17 / 144