Document Outline

• 1. Pin Descriptions
• 2. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • AnalogCharacteristics
  • Digital Interface Characteristics
  • Mute Switching Characteristics
  • Control Port Switching Characteristics - I·C Format
    • Figure 1. Control Port Timing - I·C Format
  • Control Port Switching Characteristics - SPI™ Format
    • Figure 2. Control Port Timing - SPI Format
• 3. Typical Connection Diagram
  • Figure 3. Typical Connection Diagram
• 4. Detailed Block Diagram
  • Figure 4. Detailed Block Diagram
• 5. Applications
  • 5.1 General Description
  • 5.2 System Design
    • 5.2.1 Analog Inputs
    • 5.2.2 Analog Outputs
    • 5.2.3 Recommended Layout, Grounding, and Power Supply Decoupling
  • 5.3 Power-Up and Power-Down
    • 5.3.1 Recommended Power-Up Sequence
    • 5.3.2 Recommended Power-Down Sequence
  • 5.4 Volume & Muting Control Architecture
    • 5.4.1 Control Mapping Matrix
      • Figure 5. CS3318 Control Mapping Matrix
    • 5.4.2 Volume & Muting Control Implementation
      • Figure 6. Volume & Muting Control Implementation
  • 5.5 Volume Controls
    • 5.5.1 Individual Channel Volume Controls
    • 5.5.2 Master Volume Controls
      • Table 1. Example Volume Settings
    • 5.5.3 Volume Limits
  • 5.6 Muting Controls
    • 5.6.1 Individual Channel Mute Controls
    • 5.6.2 Master Mute Controls
    • 5.6.3 Hardware Mute Control
  • 5.7 Zero-Crossing Detection
    • 5.7.1 Zero-Crossing Modes
      • Table 2. Zero-Crossing Modes
    • 5.7.2 Zero-Crossing Time-Out
      • Table 3. Zero-Crossing Time-Out Periods
  • 5.8 System Serial Control Configuration
    • 5.8.1 Serial Control within a Single-CS3318 System
      • Figure 7. Standard I·C Connections
      • Figure 8. Standard SPI Connections
    • 5.8.2 Serial Control within a Multiple-CS3318 System
      • Figure 9. SPI Serial Control Connections
      • Figure 10. Individual Device Address Configuration Process
      • Figure 11. I·C Serial Control Connections
  • 5.9 I·C/SPI Serial Control Formats
    • 5.9.1 I·C Mode
      • Table 4. I·C Mode Default Chip Address
      • Figure 12. Control Port Timing, I·C Write
      • Figure 13. Control Port Timing, I·C Read
    • 5.9.2 SPI Mode
      • Figure 14. SPI Write Cycle
• 6. CS3318 Register Quick Reference
• 7. CS3318 Register Descriptions
  • 7.1 Ch 1-8 Volume - Addresses 01h - 08h
    • 7.1.1 Volume Control (Bits 7:0)
      • Table 5. Example Volume Settings
  • 7.2 ¹dB Control - Address 09h
    • 7.2.1 ¹dB Control (Bit 0 - 7)
      • Table 6. Example Volume Settings
  • 7.3 Mute Control - Address 0Ah
    • 7.3.1 Mute Channel X (Bit 0 - 7)
  • 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
    • 7.4.1 Enable MUTE Input (Bit 5)
    • 7.4.2 MUTE Input Polarity (Bit 4)
    • 7.4.3 Channel B = Channel A (Bit 0 - 3)
      • Table 7. Channel B = Channel A Settings
  • 7.5 Device Configuration 2 - Address 0Ch
    • 7.5.1 Zero-Crossing Time-Out Period (Bits 4:2)
      • Table 8. Zero-Crossing Time-Out Settings
    • 7.5.2 Zero-Crossing Mode (Bits 1:0)
      • Table 9. Zero-Crossing Mode Settings
  • 7.6 Channel Power - Address 0Dh
    • 7.6.1 Power Down Channel X (Bit 0 - 7)
  • 7.7 Master Power - Address 0Eh
    • 7.7.1 Power Down All (Bit 0)
  • 7.8 Freeze Control - Address 0Fh
    • 7.8.1 Freeze (Bit 7)
  • 7.9 Master1 Mask - Address 10h
  • 7.10 Master1 Volume - Address 11h
    • 7.10.1 Master1 Volume Control (Bits 7:0)
  • 7.11 Master1 Control - Address 12h
    • 7.11.1 Master1 Mute (Bit 1)
    • 7.11.2 Master1 ¹dB Control (Bit 0)
  • 7.12 Master2 Mask - Address 13h
  • 7.13 Master2 Volume - Address 14h
    • 7.13.1 Master2 Volume Control (Bits 7:0)
  • 7.14 Master2 Control - Address 15h
    • 7.14.1 Master2 Mute (Bit 1)
    • 7.14.2 Master2 ¹dB Control (Bit 0)
  • 7.15 Master3 Mask - Address 16h
  • 7.16 Master3 Volume - Address 17h
    • 7.16.1 Master3 Volume Control (Bits 7:0)
  • 7.17 Master3 Control - Address 18h
    • 7.17.1 Master3 Mute (Bit 1)
    • 7.17.2 Master3 ¹dB Control (Bit 0)
  • 7.18 Group2 Chip Address 19h
    • 7.18.1 Group2 Chip Address (Bits 7:1)
    • 7.18.2 Enable Group2 Address (Bit 0)
  • 7.19 Group1 Chip Address 1Ah
    • 7.19.1 Group1 Chip Address (Bits 7:1)
    • 7.19.2 Enable Group1 Address (Bit 0)
  • 7.20 Individual Chip Address 1Bh
    • 7.20.1 Individual Chip Address (Bits 7:1)
    • 7.20.2 Enable Next Device (Bit 0)
  • 7.21 Chip ID - Address 1Ch
    • 7.21.1 Chip ID (Bits 7:4)
    • 7.21.2 Chip Revision (Bits 3:0)
      • Table 10. Chip Revision Register Codes
• 8. Parameter Definitions
• 9. Package Dimensions
• 10. Thermal Characteristics and Specifications
• 11. Ordering Information
• 12. Revision History