Document Outline

• 1. Pin Description
  • Figure 1. CS5364 Pinout
• 2. Typical Connection Diagram
  • Figure 2. Typical Connection Diagram
• 3. Characteristics and Specifications
  • Recommended Operating Conditions
  • Absolute Ratings
  • System Clocking
  • DC Power
  • Logic Levels
  • PSRR, Vq and FILT+ Characteristics
  • Analog Characteristics (Commercial)
  • Analog Performance (Automotive)
  • Digital Filter Characteristics
  • Overflow Timeout
  • Serial Audio Interface - I²S/LJ Timing
    • Figure 3. I²S/LJ Timing
  • Serial Audio Interface - TDM Timing
    • Figure 4. TDM Timing
  • Switching Specifications - Control Port - I²C Timing
    • Figure 5. I²C Timing
  • Switching Specifications - Control Port - SPI Timing
    • Figure 6. SPI Timing
• 4. Applications
  • 4.1 Power
    • Table 1. Power Supply Pin Definitions
  • 4.2 Control Port Mode and Stand-Alone Operation
    • 4.2.1 Stand-Alone Mode
    • 4.2.2 Control Port Mode
  • 4.3 Master Clock Source
    • 4.3.1 On-Chip Crystal Oscillator Driver
      • Figure 7. Crystal Oscillator Topology
    • 4.3.2 Externally Generated Master Clock
  • 4.4 Master and Slave Operation
    • Figure 8. Master/Slave Clock Flow
    • 4.4.1 Synchronization of Multiple Devices
      • Figure 9. Master and Slave Clocking for a Multi-Channel Application
  • 4.5 Serial Audio Interface (SAI) Format
    • 4.5.1 I²S and LJ Format
      • Figure 10. I²S Format
      • Figure 11. LJ Format
    • 4.5.2 TDM Format
      • Figure 12. TDM Format
    • 4.5.3 Configuring Serial Audio Interface Format
      • Table 2. DIF1 and DIF0 Pin Settings
  • 4.6 Speed Modes
    • 4.6.1 Sample Rate Ranges
    • 4.6.2 Using M1 and M0 to Set Sampling Parameters
      • Table 3. M1 and M0 Settings
    • 4.6.3 Master Mode Clock Dividers
      • Figure 13. Master Mode Clock Dividers
    • 4.6.4 Slave Mode Audio Clocking With Auto-Detect
      • Figure 14. Slave Mode Auto-Detect Speed
  • 4.7 Master and Slave Clock Frequencies
    • Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
    • Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
    • Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
    • Table 7. Frequencies for 48 kHz Sample Rate using TDM
    • Table 8. Frequencies for 48 kHz Sample Rate using TDM
    • Table 9. Frequencies for 96 kHz Sample Rate using TDM
    • Table 10. Frequencies for 96 kHz Sample Rate using TDM
    • Table 11. Frequencies for 192 kHz Sample Rate using TDM
    • Table 12. Frequencies for 192 kHz Sample Rate using TDM
  • 4.8 Reset
    • 4.8.1 Power-Down Mode
  • 4.9 Overflow Detection
    • 4.9.1 Overflow in Stand-Alone Mode
    • 4.9.2 Overflow in Control Port Mode
  • 4.10 Analog Connections
    • Figure 15. Recommended Analog Input Buffer
  • 4.11 Optimizing Performance in TDM Mode
  • 4.12 DC Offset Control
  • 4.13 Control Port Operation
    • 4.13.1 SPI Mode
      • Figure 16. SPI Format
    • 4.13.2 I²C Mode
      • Figure 17. I²C Write Format
      • Figure 18. I²C Read Format
• 5. Register Map
  • 5.1 Register Quick Reference
  • 5.2 00h (REVI) Chip ID Code & Revision Register
  • 5.3 01h (GCTL) Global Mode Control Register
  • 5.4 02h (OVFL) Overflow Status Register
  • 5.5 03h (OVFM) Overflow Mask Register
  • 5.6 04h (HPF) High-Pass Filter Register
  • 5.7 05h Reserved
  • 5.8 06h (PDN) Power Down Register
  • 5.9 07h Reserved
  • 5.10 08h (MUTE) Mute Control Register
  • 5.11 09h Reserved
  • 5.12 0Ah (SDEN) SDOUT Enable Control Register
• 6. Filter Plots
  • Figure 19. SSM Passband
  • Figure 20. DSM Passband
  • Figure 21. QSM Passband
  • Figure 22. SSM Stopband
  • Figure 23. DSM Stopband
  • Figure 24. QSM Stopband
  • Figure 25. SSM -1 dB Cutoff
  • Figure 26. DSM -1 dB Cutoff
  • Figure 27. QSM -1 dB Cutoff
• 7. Parameter Definitions
• 8. Package Dimensions
  • Thermal Characteristics
• 9. Ordering Information
• 10. Revision History