Document Outline

• 1. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • Digital Input Characteristics
  • Digital Interface Specifications
  • Switching Characteristics
  • Switching Characteristics - Serial Audio Ports
    • Figure 1. Audio Port Master Mode Timing
    • Figure 2. Audio Port Slave Mode and Data Input Timing
  • Switching Characteristics - Control Port - SPI Mode
    • Figure 3. SPI Mode Timing
  • Switching Characteristics - Control Port - I·C Mode
    • Figure 4. I·C Mode Timing
• 2. Typical Connection Diagram
  • Figure 5. Recommended Connection Diagram for Software Mode
• 3. General Description
  • 3.1 AES3 and S/PDIF Standards Documents
• 4. Serial Audio output Port
  • Figure 6. Serial Audio Output Example Formats
• 5. AES3 Receiver
  • 5.1 7:1 S/PDIF Input Multiplexer
  • 5.2 OMCK System Clock Mode
  • 5.3 PLL, Jitter Attenuation, and Varispeed
  • 5.4 Error Reporting and Hold Function
  • 5.5 Channel Status Data Handling
  • 5.6 User Data Handling
  • 5.7 Non-Audio Auto-Detection
  • 5.8 Mono Mode Operation
    • Figure 7. AES3 ReceiverTiming for C & U Pin Output Data
• 6. Control Port Description and Timing
  • 6.1 SPITM Mode
    • Figure 8. Control Port Timing in SPI Mode
  • 6.2 I·C Mode
  • 6.3 Interrupts
    • Figure 9. Control Port Timing in I·C Mode
• 7. Control Port Register Summary
  • Table 1. Control Register Map Summary
  • 7.1 Memory Address Pointer (MAP)
• 8. Control Port Register Bit Definitions
  • 8.1 Control 1 (01h)
  • 8.2 Control 2 (02h)
  • 8.3 Clock Source Control (04h)
  • 8.4 Serial Audio Output Port Data Format (06h)
  • 8.5 Interrupt 1 Status (07h) (Read Only)
  • 8.6 Interrupt 2 Status (08h) (Read Only)
  • 8.7 Interrupt 1 Mask (09h)
  • 8.8 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
  • 8.9 Interrupt 2 Mask (0Ch)
  • 8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB (0Eh)
  • 8.11 Receiver Channel Status (0Fh) (Read Only)
  • 8.12 Receiver Error (10h) (Read Only)
  • 8.13 Receiver Error Mask (11h)
  • 8.14 Channel Status Data Buffer Control (12h)
  • 8.15 User Data Buffer Control (13h)
  • 8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)
  • 8.17 OMCK/RMCK Ratio (1Eh) (Read Only)
  • 8.18 C-bit or U-bit Data Buffer (20h - 37h)
  • 8.19 CS8415A I.D. and Version Register (7Fh) (Read Only)
• 9. Pin Description - Software Mode
• 10. Hardware Mode
  • 10.1 Serial Audio Port Formats
    • Table 2. Equivalent Software Mode Bit Definitions
    • Table 3. Hardware Mode Start-Up Options
    • Figure 10. Hardware Mode
• 11. Pin Description - Hardware Mode
• 12. Applications
  • 12.1 Reset, Power Down and Start-Up
  • 12.2 ID Code and Revision Code
  • 12.3 Power Supply, Grounding, and PCB Layout
• 13. Appendix A: External AES3/SPDIF/IEC60958 Receiver Components
  • 13.1 AES3 Receiver External Components
  • 13.2 Isolating Transformer Requirements
    • Figure 11. Professional Input Circuit
    • Figure 12. Transformerless Professional Input Circuit
    • Figure 13. Consumer Input Circuit
    • Figure 14. S/PDIF MUX Input Circuit
    • Figure 15. TTL/CMOS Input Circuit
• 14. Appendix B: Channel Status and User Data Buffer Management
  • 14.1 AES3 Channel Status (C) Bit Management
    • Figure 16. Channel Status Data Buffer Structure
  • 14.2 Accessing the E Buffer
    • Figure 17. Flowchart for Reading the E Buffer
    • 14.2.1 Reserving the First 5 Bytes in the E Buffer
    • 14.2.2 Serial Copy Management System (SCMS)
    • 14.2.3 Channel Status Data E Buffer Access
  • 14.3 AES3 User (U) Bit Management
• 15. Appendix C: PLL Filter
  • 15.1 General
    • Figure 18. PLL Block Diagram
  • 15.2 External Filter Components
    • 15.2.1 General
    • 15.2.2 Capacitor Selection
    • 15.2.3 Circuit Board Layout
      • Figure 19. Recommended Layout Example
  • 15.3 Component Value Selection
    • 15.3.1 Identifying the Part Revision
      • Table 4. Second Line Part Marking
    • 15.3.2 External Components
      • Table 5. Fs = 8 to 96kHz
      • Table 6. Fs = 32 to 96kHz
    • 15.3.3 Jitter Tolerance
      • Figure 20. Jitter Tolerance Template
    • 15.3.4 Jitter Attenuation
      • Figure 21. Revision A
      • Figure 22. Revision A1
      • Figure 23. Revision A2 using A1 Values
      • Figure 24. Revision A2 using A2* Values
• 16. Revision History