3 bypass register, 4 jtag_cfm_clkdiv register, 5 test_ctrl register – Freescale Semiconductor ColdFire MCF52210 User Manual

Page 549: 6 boundary scan register

Advertising
background image

IEEE 1149.1 Test Access Port (JTAG)

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor

29-5

29.3.3

Bypass Register

The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS instruction is
selected.

29.3.4

JTAG_CFM_CLKDIV Register

The JTAG_CFM_CLKDIV register is a 7-bit clock divider for the CFM that is used with the
LOCKOUT_RECOVERY instruction. It controls the period of the clock used for timed events in the CFM
erase algorithm. The JTAG_CFM_CLKDIV register must be loaded before the lockout sequence can
begin.

29.3.5

TEST_CTRL Register

The TEST_CTRL register is a 3-bit shift register path from TDI to TDO when the
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold
register on the rising edge of TCLK when the TAP state machine is in the update-DR state.

29.3.6

Boundary Scan Register

The boundary scan register is connected between TDI and TDO when the EXTEST or
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins,
and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.

IR[4:0]: 0_0001 (IDCODE)

Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

R

PRN

DC

PIN

JEDEC

ID

W

Reset

See note

1

0

1

1

1

0

1

See note

1

0

0

0

0

0

0

0

1

1

1

0

1

1

The reset values for PRN and PIN are device-dependent.

Figure 29-3. IDCODE Register

Table 29-4. IDCODE Field Descriptions

Field

Description

31–28

PRN

Part revision number. Indicate the revision number of the device.

27–22

DC

Freescale Design Center number.

21–12

PIN

Part identification number. Indicate the device number.

11–1

JEDEC

Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E).

0

ID

IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register
according to the IEEE standard 1149.1.

Advertising
This manual is related to the following products: