Lenze EVS9332xS User Manual
Ä.fz9ä, Global drive
Advertising
This manual is related to the following products:
Table of contents
Document Outline
- Servo inverter 9300
- Contents
- 1 Preface
- 2 Configuration
- 2.4 Change of the terminal assignment
- 3 Function library
- 3.1 Working with function blocks
- 3.2 Function blocks
- 3.2.1 Table of function blocks
- 3.2.2 Table of free control codes
- 3.2.3 Addition block (ADD)
- 3.2.4 Automation interface (AIF-IN)
- 3.2.5 Automation interface (AIF-OUT)
- 3.2.6 Analog inputs via terminal X6/1, X6/2 and X6/ 3, X6/4 (AIN)
- 3.2.7 AND operation (AND)
- 3.2.8 Inverter (ANEG)
- 3.2.9 Analog output via terminal 62/63 (AOUT)
- 3.2.10 Arithmetic block (ARIT)
- 3.2.11 Arithmetic block (ARITPH)
- 3.2.12 Analog signal changeover switch (ASW)
- 3.2.13 Holding brake (BRK)
- 3.2.14 System bus (CAN-IN)
- 3.2.15 System bus (CAN-OUT)
- 3.2.16 Comparator (CMP)
- 3.2.17 Signal conversion (CONV)
- 3.2.18 Angle conversion (CONVPHA)
- 3.2.19 Angle conversion (CONVPHPH)
- 3.2.20 Speed conversion (CONVPP)
- 3.2.21 Characteristic function (CURVE)
- 3.2.22 Dead band (DB)
- 3.2.23 Control of the drive controller (DCTRL)
- 3.2.24 Master frequency input (DFIN)
- 3.2.25 Digital frequency output (DFOUT)
- 3.2.26 Digital frequency ramp function generator (DFRFG)
- 3.2.27 Digital frequency processing (DFSET)
- 3.2.28 Delay elements (DIGDEL)
- 3.2.29 Freely assignable digital inputs (DIGIN)
- 3.2.30 Freely assignable digital outputs (DIGOUT)
- 3.2.31 First order derivative-action element (DT1)
- 3.2.32 Free piece counter (FCNT)
- 3.2.33 Free digital outputs (FDO)
- 3.2.34 Freely assignable input variables (FEVAN)
- 3.2.35 Fixed setpoints (FIXSET)
- 3.2.36 Flipflop element (FLIP)
- 3.2.37 Gearbox compensation (GEARCOMP)
- 3.2.38 Limiting element (LIM)
- 3.2.39 Internal motor control (MCTRL)
- 3.2.40 Mains failure control (MFAIL)
- 3.2.41 Motor phase failure detection (MLP)
- 3.2.42 Monitor outputs of monitoring system (MONIT)
- 3.2.43 Motor potentiometer (MPOT)
- 3.2.44 Logic NOT
- 3.2.45 Speed setpoint conditioning (NSET)
- 3.2.46 OR operation (OR)
- 3.2.47 Oscilloscope function (OSZ)
- 3.2.48 Process controller (PCTRL1)
- 3.2.49 Angle addition block (PHADD)
- 3.2.50 Angle comparator (PHCMP)
- 3.2.51 Actual angle integrator (PHDIFF)
- 3.2.52 Signal adaptation for angle signals (PHDIV)
- 3.2.53 Phase integrator (PHINT)
- 3.2.54 Delay element (PT1-1)
- 3.2.55 CW/CCW/QSP linking (R/L/Q)
- 3.2.56 Homing function (REF)
- 3.2.57 Ramp function generator (RFG)
- 3.2.58 Sample and hold function (S&H)
- 3.2.59 S-shaped ramp function generator (SRFG)
- 3.2.60 Output of digital status signals (STAT)
- 3.2.61 Control of a drive network (STATE-BUS)
- 3.2.62 Storage block (STORE)
- 3.2.63 Multi-axis synchronisation (SYNC1)
- 3.2.64 Edge evaluation (TRANS)
- 4 Application examples
- 5 Appendix