Overview, General description, Board component blocks – Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Manual
Page 5: Chapter 1. overview, General description –1 board component blocks –1
May 2014
Altera Corporation
Transceiver Signal Integrity Development Kit
Stratix V GT Edition Reference Manual
1. Overview
This document describes the hardware features of the Stratix
®
V GT transceiver signal
integrity development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Transceiver Signal Integrity Development Kit, Stratix V GT Edition, allows you to
evaluate the performance of the Stratix V GT FPGA which is optimized for
high-performance and high-bandwidth applications with integrated transceivers
supporting backplane, chip-to-chip, and chip-to-module operation.
f
For more information on the following topics, refer to the respective documents:
■
Setting up the development board and using the included software, refer to the
.
■
Stratix V device family, refer to the
.
Board Component Blocks
The Stratix V GT transceiver signal integrity development board provides a hardware
platform for evaluating the performance and signal integrity features of the Altera
®
Stratix V GT device. The development board features the following major component
blocks:
■
Altera Stratix V GT FPGA (5SGTMC7K2F40C2) in a 1517-pin FineLine BGA
package
■
622,000 LEs
■
234,720 adaptive logic modules (ALMs)
■
50-Mbits (Mb) embedded memory
■
512 18x18-bit multipliers
■
36 transceivers (32 channels with 12.5 Gbps and four channels with 28 Gbps)
■
174 LVDS transmit channels
■
28 phase locked loops (PLLs)
■
696 user I/Os
■
850-mV core voltage