Inova High Performance CPU board ICP-PII - Manual (Page 25)

©2002 Inova Computers GmbH Page 2-1 Doc. PD00581013.004
ICP-PIII Configuration
CompactPCI
®
2
Configuration
Configuration Con-
tents
2.0 Memory Map ........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
Table 2.00 UMB Reservations for ISA ......................................................................................... 2-3
Table 2.01 Port Addressing ........................................................................................................ 2-3
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
2.2 Memory Mapped Peripherals ..... 2-5
2.3 Interrupt Routing .................... 2-5
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-6
2.4 Inova PIII Device List ................ 2-7
Table 2.40 Legacy I/O Map (ISA Compatible) ............................................................................ 2-7
2.5 Interrupt Configuration ............ 2-8
Table 2.50 CompactPCI Bus Interrupts ....................................................................................... 2-8
2.6 Timer / Counter ....................... 2-9
2.7 Watchdog ............................... 2-9