4 testability port signals – Intel GD82559ER User Manual
Page 16
GD82559ER — Networking Silicon
10
Datasheet
3.4
Testability Port Signals
FLA[13]/
EEDI
OUT
Flash Address[13]/EEPROM Data Input. During Flash accesses,
this multiplexed pin acts as the Flash Address [13] output signal.
During EEPROM accesses, it acts as serial output data to the
EEPROM Data Input signal.
FLA[12:8]
OUT
Flash Address[12:8]. These pins are used as Flash address outputs
to support 128 Kbyte Flash addressing.
FLA[7]/
CLKENB
T/S
Flash Address[7]/Clock Enable. This is a multiplexed pin and acts
as the Flash Address[7] output signal during nominal operation. When
the PCI RST# signal is active, this pin acts as input control over the
FLA[16]/CLK25 output signal. If the FLA[7]/CLKEN pin is connected to
a pull-up resistor (3.3 K
Ω
), a 25 MHz clock signal is provided on the
FLA[16]/CLK25 output; otherwise, it is used as FLA[16] output.
FLA[6:2]
OUT
Flash Address[6:2]. These pins are used as Flash address outputs
to support 128 Kbyte Flash addressing.
FLA[1]/
AUXPWR
T/S
Flash Address[1]/Auxiliary Power. This multiplexed pin acts as the
Flash Address[1] output signal during nominal operation. When RST is
active (low), it acts as the power supply indicator. If the 82559ER is fed
PCI power, this pin should be connected to a pull-down resistor; if the
82559ER is fed by auxiliary power, this pin should be connected to a
pull-up resistor.
FLA[0]
T/S
Flash Address [0]. This pin acts as the Flash Address[0] output
signal during nominal operation.
EECS
OUT
EEPROM Chip Select. The EEPROM Chip Select signal is used to
assert chip select to the serial EEPROM.
FLCS#
OUT
Flash Chip Select. The Flash Chip Select signal is active during
Flash.
FLOE#
OUT
Flash Output Enable. This pin provides an active low output enable
control (read) to the Flash memory.
FLWE#
OUT
Flash Write Enable. This pin provides an active low write enable
control to the Flash memory.
Symbol
Type
Name and Function
Symbol
Type
Name and Function
TEST
IN
Test. If this input pin is high, the 82559ER will enable the test port.
During nominal operation this pin should be connected to a pull-down
resistor.
TCK
IN
Testability Port Clock. This pin is used for the Testability Port Clock
signal.
TI
IN
Testability Port Data Input. This pin is used for the Testability Port
Data Input signal.
TEXEC
IN
Testability Port Execute Enable. This pin is used for the Testability
Port Execute Enable signal.
TO
OUT
Testability Port Data Output. This pin is used for the Testability Port
Data Output signal.