National Instruments NI PCI-6110 - Manual (Page 55)

Chapter 4 Connecting Signals
© National Instruments Corporation 4-25 NI PCI-6110/6111 User Manual
Figure 4-18. CONVERT* Output Signal Timing
The ADC switches to hold mode within 20 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
one conversion to the next.
The SI2 on the NI PCI-6110/6111 normally generates CONVERT* unless
you select some external source. The counter is started by the
STARTSCAN signal and continues to count down and reload itself until the
scan is finished. It then reloads itself in preparation for the next
STARTSCAN pulse.
A/D conversions generated by either an internal or external CONVERT*
signal are inhibited unless they occur within a DAQ sequence. Scans
occurring within a DAQ sequence may be gated by either the hardware
(AIGATE) signal or software command register gate.
AIGATE Signal
Any PFI pin can receive as an input the AIGATE signal, which is not
available as an output on the I/O connector. The AIGATE signal can mask
off scans in a DAQ sequence. You can configure the PFI pin you select as
the source for the AIGATE signal in either the level-detection or
edge-detection mode. You can configure the polarity selection for the
PFI pin for either active high or active low.
In the level-detection mode if AIGATE is active, the STARTSCAN signal
is masked off and no scans can occur. In the edge-detection mode, the first
active edge disables the STARTSCAN signal, and the second active edge
enables STARTSCAN.
AIGATE can neither stop a scan in progress nor continue a previously
gated-off scan. Once a scan has started, AIGATE does not gate off
conversions until the beginning of the next scan and, conversely, if
conversions are being gated off, AIGATE does not gate them back on until
the beginning of the next scan.
t
w
= 50 to 100 ns
t
w