Rainbow Electronics MAX9671 - Manual (Page 19)

MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
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REPEATED START (Sr) condition, an acknowledge or a
not acknowledge, and a STOP (P) condition. SDA oper-
ates as both an input and an open-drain output. A
pullup resistor, typically greater than 500
Ω, is required
on the SDA bus. SCL operates as only an input. A
pullup resistor, typically greater than 500
Ω, is required
on SCL if there are multiple masters on the bus, or if the
master in a single-master system has an open-drain
SCL output. Series resistors in line with SDA and SCL
are optional. Series resistors protect the digital inputs of
the MAX9670/MAX9671 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions section). SDA and SCL idle high when the
I 2 C bus is not busy.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START (S)
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9670/MAX9671. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Early STOP Conditions
The MAX9670/MAX9671 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9670/MAX9671 to
read mode. Set the R/W bit to 0 to configure the
MAX9670/MAX9671 to write mode. The slave address
is always the first byte of information sent to the
MAX9670/MAX9671 after a START or a REPEATED
START condition. The MAX9670/MAX9671 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the
MAX9670/MAX9671.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
t
HD, STA
t SU, STA
t HD, STA t SP
t BUF
t SU, STO t LOW
t SU, DAT
t HD, DAT
t HIGH
t R t F
Figure 6. I 2 C Serial-Interface Timing Diagram
SCL
SDA
S Sr P
Figure 7. START, STOP, and REPEATED START Conditions