MagTek TRIPLE TRACK Delta ASIC - Manual (Page 10)

Triple Track ASIC
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is cleared will keep the ASIC awake, but this partial swipe will not be stored, and there will not be any
signal given on the DATA line pertaining to this partial swipe other than the extension of Tsc discussed
above. Such a “swipe-in-progress” at the time of a memory clear operation has to end before the ASIC
will “re-arm” to be ready for a new swipe. Note that if the data is extracted quickly after receiving the
ZEROES FLAG, the magnetic stripe with its remaining zero-bits may still be passing under the magnetic
head. Thus, it may appear that Tsc (see “Shift-Out Timing”) is excessively long when in fact there is a
“swipe-in-progress” delaying the response of DATA. This may be an important consideration when
designing a “dip” or “insert” reader, and a fast turnaround is required to read on both insertion and
withdrawal.
The check for “swipe-in-progress” will not be enforced in future revisions of this ASIC. The ASIC will
re-arm quickly after its memory has been cleared. Partial swipes will be reported, although the report
may be erroneous in cases where an adequate number of leading zero-bits was not available for
synchronization.
The ASIC features circuitry that filters most ambient noise and prevents “bothering” the controller
needlessly when there has been no card swipe. The signal from the magnetic head must first meet certain
amplitude and frequency characteristics before any data is stored in the buffer. The ASIC must be able to
establish a sufficiently stable bit-cell time-base from an adequate number of consecutive zero-bits before
decoding can proceed.
Also the length of the binary data (including all zero-bits) following and including the first one-bit must
exceed 32 bits, or the swipe for that track may be ignored.
The 32-bit limit will not be enforced in future revisions of this ASIC. There will be no lower limit on the
length of the data.