Cirrus Logic CS5368 User Manual
Cs5368, Features, Additional control port features
Copyright
Cirrus Logic, Inc. 2014
(All Rights Reserved)
114 dB, 192 kHz, 8-Channel A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-Bit Conversion
114 dB Dynamic Range
-105 dB THD+N
Supports Audio Sample Rates up to 216 kHz
Selectable Audio Interface Formats
– Left-Justified, I²S, TDM
– 8-Channel TDM Interface Formats
Low Latency Digital Filter
Less than 680 mW Power Consumption
On-Chip Oscillator Driver
Operation as System Clock Master or Slave
Auto-Detect Speed in Slave Mode
Differential Analog Architecture
Separate 1.8 V to 5 V Logic Supplies for
Control and Serial Ports
High-Pass Filter for DC Offset Calibration
Overflow Detection
Footprint Compatible with the 4-Channel
CS5364 and 6-Channel CS5366
Additional Control Port Features
Supports I²C or SPI™ Control Interface per
and
Individual Channel HPF Disable
Overflow Detection for Individual Channels
Mute Control for Individual Channels
Independent Power-Down Control per Channel
Pair
Digital
Audio
Voltage
Reference
Le
ve
l
Tra
nslator
Lev
e
l
Tr
an
sl
a
to
r
Internal
Oscillator
VD
3.3 - 5V
Control Interface
I2C, SPI
or Pins
Configuration
Registers
VA
5V
VLC
1.8 - 5V
VLS
1.8 - 5V
8 Differential
Analog Inputs
Device
Control
Serial
Audio Out
PCM or
TDM
Decimation
Filter
High Pass
Filter
Multi-bit
ADC
CS5368
JUL '14
DS624F5
Document Outline
- 1. Pin Description
- 2. Typical Connection Diagram
- 3. Characteristics and Specifications
- Recommended Operating Conditions
- Absolute Ratings
- System Clocking
- DC Power
- Logic Levels
- PSRR, Vq and FILT+ Characteristics
- Analog Characteristics (Commercial)
- Analog Characteristics (Automotive)
- Digital Filter Characteristics
- Overflow Timeout
- Serial Audio Interface - I²S/LJ Timing
- Serial Audio Interface - TDM Timing
- Switching Specifications - Control Port - I²C Timing
- Switching Specifications - Control Port - SPI Timing
- 4. Applications
- 4.1 Power
- 4.2 Control Port Mode and Stand-Alone Operation
- 4.3 Master Clock Source
- 4.4 Master and Slave Operation
- 4.5 Serial Audio Interface (SAI) Format
- 4.6 Speed Modes
- 4.7 Master and Slave Clock Frequencies
- Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
- Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
- Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
- Table 7. Frequencies for 48 kHz Sample Rate using TDM
- Table 8. Frequencies for 48 kHz Sample Rate using TDM
- Table 9. Frequencies for 96 kHz Sample Rate using TDM
- Table 10. Frequencies for 96 kHz Sample Rate using TDM
- Table 11. Frequencies for 192 kHz Sample Rate using TDM
- Table 12. Frequencies for 192 kHz Sample Rate using TDM
- 4.8 Reset
- 4.9 Overflow Detection
- 4.10 Analog Connections
- 4.11 Optimizing Performance in TDM Mode
- 4.12 DC Offset Control
- 4.13 Control Port Operation
- 5. Register Map
- 5.1 Register Quick Reference
- 5.2 00h (REVI) Chip ID Code & Revision Register
- 5.3 01h (GCTL) Global Mode Control Register
- 5.4 02h (OVFL) Overflow Status Register
- 5.5 03h (OVFM) Overflow Mask Register
- 5.6 04h (HPF) High-Pass Filter Register
- 5.7 05h Reserved
- 5.8 06h (PDN) Power Down Register
- 5.9 07h Reserved
- 5.10 08h (MUTE) Mute Control Register
- 5.11 09h Reserved
- 5.12 0Ah (SDEN) SDOUT Enable Control Register
- 6. Filter Plots
- 7. Parameter Definitions
- 8. Package Dimensions
- 9. Ordering Information
- 10. Revision History