Cirrus Logic CRD5381 - Manual (Page 9)

DS563RD1 9
CRD5381
2. OPERATION
2.1 Sample Rate
Sampling Clock Domain - The Sampling clock domain includes the CS5381 A/D converter and the serial
audio input to the CS8421 SRC. The sampling frequency in this clock domain is dictated by the ILRCK fre-
quency of each CS8421, and is derived from the system master clock Y2. The sample rate within this clock
domain is fixed at 195.312 kHz.
Interface Clock Domain - The Interface clock domain includes the output of the CS8421 SRC. The sample
rate of this domain is dictated by the frequency of the Left/Right or Word clock. This signal is an input to the
system and must be applied by the user through header J4.
2.2 Audio Data Output Format Selection
The CRD5381 allows selection of either a standard Left-Justified 3-wire serial audio interface with sepa-
rate data lines for each ADC / SRC pair or a 4-channel TDM interface. Selection of either mode is accom-
plished via jumper J8. The two possible serial audio output formats are shown in
Figures 4 and 5 .
Figure 4. Left-Justified Serial Audio Interface
Figure 5. TDM Audio Interface
2.3 System Clocking and Data I/O
Serial Clock - The Serial Clock must be applied by the user through header J4 in both Left-Justified and
TDM mode. In TDM mode, Serial Clock must be 128*Left/Right Clock.
Left /Right or Word Clock - The Left/Right Clock must be applied by the user through header J4 in both
Left-Justified and TDM mode. The output sample rate is determined by the frequency of this clock.
Serial Data Output - The serial data is output on J4. Separate stereo data outputs are available as
SDOUT A and TDM/SDOUT B when the Left-Justified format is selected. Four-channel TDM data is avail-
able on TDM/SDOUT B (J4) when the TDM mode is selected.
Figure 4 and Figure 5 illustrate Left-Justified and TDM data structures. Please refer to the “Slave Mode
Switching Specifications” on page 8 of the CS8421 data sheet for the timing requirements of both the Left-
Justified and TDM modes[3].
Figure 6 illustrates the clock and data connections to J4.
LRCK INPUT
SCLK INPUT
SDOUT
Channel A Channel B
MSB MSB LSB LSB MSB
LRCK
INPUT
SCLK
INPUT
MSB MSB MSB
TDM/
SDOUT B
SDOUT A (Left)
32 clks 32 clks 32 clks
MSB
32 clks
SDOUT A (Right) SDOUT B (Left) SDOUT B (Right)