Cirrus Logic AN372 - Manual (Page 25)

AN372
AN372REV1 25
The maximum FET voltage is calculated using Equation 38:
where
V
D3
= Forward voltage across catch diode D3.
Examining the result reveals two problem areas:
1. The FET peak current I
PK(FB)
is 30 times the average current I
AV
, requiring the FET to carry and switch a
substantial current.
2. Period T1 is short, just under 0.5 s. At low power, when the peak current I
PK(FB)
is reduced by half, period
T1 must be reduced to nearly 200ns.
A power FET does not respond well to narrow pulses, so the CS1612/13 controller has a minimum gate drive
time set to 0.5µs. Furthermore, period T1 granularity is 50ns causing the control to become jittery at narrow
pulse widths. The given requirements cannot be met with a normal buck approach.
The example shows the limitations of a normal buck approach. If a higher load voltage, lower boost voltage,
and/or switching frequency apply, then the normal buck approach could be a viable solution.
Tapped Buck Circuit Design
The requirements dictate the design to be a tapped buck.
Step 2) Select a Value for Boost Output Voltage
The example design is a 230V application. The boost output voltage, V
BST
, is 405V nominal. The CS1613
limits the boost output voltage to +10%. Maximum boost output voltage, V
BST(max)
, is calculated using
Equation 39:
Step 3) Select an Appropriate FET
Buck converters have an optimal operating range above 50% duty cycle, although anything above 30% is
close to optimal. A 50% duty cycle implies that the FET Q4 maximum drain voltage V
DS(max)
is calculated using
Equation 40:
requiring a 900V FET.
It is desirable to use a FET with a breakdown voltage of 600V and a tapped buck inductor with a turns ratio
greater than zero. The FET Q4 drain voltage V
DS
during period T2 is calculated using Equation 41:
Maintaining a 50V margin on the FET breakdown voltage:
Step 4) Determine the Buck Inductor Turns Ratio
Solving Equation 42 for turns ratio N gives Equation 43:
V
DS max  
V
BST max  
V
OUT max  
V
D3
+ + 405  V 40.5V  24  V 1.2V  1V + + + + 471.7V = = = [Eq. 38]
V
BST max  
405V = 1.1 445.5V =  [Eq. 39]
V
DS max  
2 V
BST max  
V
OUT max  
–    = 2 445V 25.2V –    840V = = [Eq. 40]
V
DS
V
BST max  
N V
OUT max  
   + = [Eq. 41]
550V 445V N 25.2  V   + = [Eq. 42]
N
550V 445V –
25.2V
---------------------------------- 4.17 = = [Eq. 43]