Cypress CY7C1347G - Manual (Page 13)

CY7C1347G
Document #: 38-05516 Rev. *F Page 13 of 22
Figure 6. Write Cycle Timing
[16, 17]
Switching Waveforms (continued)
t CYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
BWE,
BW[A :B]
Data Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH tADS
tADH tADS
t
OEHZ
t
ADVH
t
ADVS
tWEH tWES
tDH tDS
GW
tWEH tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
Note
17. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW
x
LOW.
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