Altera GPIO - Manual (Page 22)

To generate simulation design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported simulation tools.
Each subdirectory contains the specific scripts to run simulation with the corresponding tool.
The simulation design example is made of a driver connected to the generated IP. The driver generates
random traffic and internally checks the legality of the out going data.
Document Revision History
Date Version Changes
August, 2014 2014.08.18 • Added timing information.
• Added register packing information.
• Added Use legacy top-level port names parameter. This is a new
parameter.
• Added register packing information.
• Replaced the term megafunction with IP core.
November,
2013
2013.11.29 Initial release.
22 Document Revision History
ug-altera_gpio
2014.08.18
Altera Corporation Altera GPIO IP Core User Guide
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