Altera Phase-Locked Loop - Manual

Altera Phase-Locked Loop (Altera PLL) IP Core User
Guide
2015.05.04
UG-01087 Subscribe Send Feedback
The Altera PLL megafunction IP core allows you to configure the settings of PLL.
Altera PLL IP core supports the following features:
• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buffer, and LVDS mode.
• Generates up to 18 clock output signals for the Arria ® V and Stratix ® V devices and nine clock output
signals for the Cyclone ® V device.
• Switches between two reference input clocks.
• Supports both the adjacent PLL (
adjpllin
) and the
C
-Counter clock source (
cclk
) inputs to connect
with an upstream PLL in PLL cascading mode.
• Supports PLL output cascading.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
Related Information
• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.
• Operation Modes on page 9
• Output Clocks on page 9
• Reference Clock Switchover on page 10
• PLL-to-PLL Cascading on page 10
• PLL Output Counter Cascading on page 14
Device Family Support
The Altera PLL IP core supports the Arria V, Cyclone V, and Stratix V device families.
Altera PLL IP Core Parameters
The Altera PLL IP core parameter editor appears in the PLL category of the IP Catalog.
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