Altera PHYLite - Manual

Altera PHYLite for Parallel Interfaces IP Core User
Guide
2015.01.16
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The Altera PHYLite for Parallel Interfaces IP core controls the strobe-based capture I/O elements in
Arria ® 10 devices. Use each instance of the IP core to support an interface with up to 18 individual data/
strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic.
Device Family Support
The Altera PHYLite for Parallel Interfaces IP core supports Arria ® 10 devices only.
For Arria V, Cyclone ® V, and Stratix ® V devices, use the ALTDQ_DQS2 IP core instead.
Related Information
• ALTDQ_DQS2 IP Core User Guide
For more information about the ALTDQ_DQS2 IP core
Features
The Altera PHYLite for Parallel Interfaces IP core:
• Supports input, output, and bidirectional data channels
• Supports DQS-group based data capture, with up to 48 I/Os (including strobes) per group and DQS
gating/ungating circuitry for strobe-based interfaces
• Supports output delays via interpolator
• Supports dynamic on-chip termination (OCT) control
• Supports quarter-rate to half-rate and half-rate to full-rate conversions. Also supports input, output,
and read/DQS/OCT enable paths
• Supports single data rate (SDR) and double data rate (DDR) at the I/Os
• Supports PHY clock tree
• Supports dynamically reconfigurable delay chains using Avalon interface
• Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay
chains
Note: The non-PVT compensated component of the input delay is not set in the Quartus II software
version 14.1 and will only be set in a future release of the Quartus II software.
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