Altera ALTPLL (Phase-Locked Loop) IP Core User Manual
Page 55
Description
Type
Parameter
Specifies the operation of the PLL. Values are
EXTERNAL_
FEEDBACK
,
NO_COMPENSATION
,
NORMAL
,
ZERO_DELAY_
BUFFER
, and
SOURCE_SYNCHRONOUS
. If omitted, the default
is
NORMAL
.
• In no compensation mode, the PLL does not align a
clock to the input, which leads to better jitter
performance.
• In source-synchronous mode, the clock delay from pin
to I/O input register matches the data delay from pin
to I/O input register.
• Source-synchronous mode allows the clock delay from
pin to I/O input register to match the data delay from
pin to I/O input register.
• In normal mode, the PLL compensates for the delay of
the internal clock network used by the clock output
specified in the
COMPENSATE_CLOCK
parameter. If the
PLL is also used to drive an external clock output pin,
a corresponding phase shift of the output pin results.
• In zero-delay buffer mode, the PLL must feed an
external clock output pin and compensate for the delay
introduced by that pin. The signal observed on the pin
is synchronized to the input clock. If the PLL is also
used to drive the internal clock network, a
corresponding phase shift of that network results.
• In external feedback mode, the
fbin
input port must
be connected to an input pin, and there must be a
board-level connection between this input pin and an
external clock output pin, which is specified with
FEEDBACK_SOURCE
parameter. The
fbin
port is aligned
with the input clock. Use the maximum input delay
assignment on the
fbin
port to specify external board
delay.
Note that for source-synchronous mode and zero-delay
buffer mode, you need to make assignments (in this case,
the PLL_COMPENSATE assignment) in addition to setting
the appropriate mode in the IP core. This allows you to
specify an output pin as a compensation target for a PLL
in zero-delay buffer or external feedback mode, or an input
pin or a group of input pins as compensation targets for a
PLL in Source- Synchronous mode.
If assigned to an output pin, the pin must be fed by the
external clock output port of a PLL in a Stratix, HardCopy
Stratix or Cyclone device, or the compensated clock output
port of a PLL in other devices. Any other output pins fed
by the same PLL generally are not delay compensated,
especially if they have different I/O standards.
If assigned to an input pin or a group of input pins, the
input pins must drive input registers that are clocked by
Altera Corporation
ALTPLL (Phase-Locked Loop) IP Core User Guide
55
ALTPLL Parameters
ug-altpll
2014.08.18