Contents
About the NCO IP Core...................................................................................... 1-1
Altera DSP IP Core Features...................................................................................................................... 1-1
NCO IP Core Features................................................................................................................................ 1-2
DSP IP Core Device Family Support.........................................................................................................1-2
NCO IP Core MegaCore Verification.......................................................................................................1-3
NCO IP Core Release Information............................................................................................................1-3
NCO IP Core Performance and Resource Utilization............................................................................1-4
NCO IP Core Getting Started............................................................................. 2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
NCO IP Core OpenCore Plus Timeout Behavior....................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-5
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-8
DSP Builder Design Flow............................................................................................................................2-9
NCO IP Core Functional Description................................................................ 3-1
NCO IP Core Architectures....................................................................................................................... 3-2
Large ROM Architecture................................................................................................................ 3-2
Small ROM Architecture................................................................................................................ 3-2
CORDIC Architecture.....................................................................................................................3-3
Multiplier-Based Architecture....................................................................................................... 3-4
Multichannel NCOs.....................................................................................................................................3-5
Frequency Hopping.....................................................................................................................................3-5
Phase Dithering............................................................................................................................................3-6
Frequency Modulation................................................................................................................................3-7
Phase Modulation........................................................................................................................................ 3-7
NCO IP Core Parameters........................................................................................................................... 3-7
Architecture Parameters................................................................................................................. 3-7
Frequency Parameters.....................................................................................................................3-8
Optional Ports Parameters..............................................................................................................3-9
NCO IP Core Interfaces and Signals.........................................................................................................3-9
Avalon-ST Interfaces in DSP IP Cores..........................................................................................3-9
NCO IP Core Signals.....................................................................................................................3-10
NCO IP Core Timing Diagrams..................................................................................................3-11
NCO Multichannel Design Example...................................................................4-1
NCO Design Example Specification..........................................................................................................4-2
TOC-2
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