Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 60)

2–52 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
P7 DDR3E_A1 1.5-V SSTL A29 Address bus
P3 DDR3E_A2 1.5-V SSTL V27 Address bus
N2 DDR3E_A3 1.5-V SSTL R27 Address bus
P8 DDR3E_A4 1.5-V SSTL T27 Address bus
P2 DDR3E_A5 1.5-V SSTL C28 Address bus
R8 DDR3E_A6 1.5-V SSTL M23 Address bus
R2 DDR3E_A7 1.5-V SSTL T31 Address bus
T8 DDR3E_A8 1.5-V SSTL P23 Address bus
R3 DDR3E_A9 1.5-V SSTL V29 Address bus
L7 DDR3E_A10 1.5-V SSTL H23 Address bus
R7 DDR3E_A11 1.5-V SSTL N23 Address bus
N7 DDR3E_A12 1.5-V SSTL L24 Address bus
T3 DDR3E_A13 1.5-V SSTL Y32 Address bus
M2 DDR3E_BA0 1.5-V SSTL L30 Bank address bus
N8 DDR3E_BA1 1.5-V SSTL J25 Bank address bus
M3 DDR3E_BA2 1.5-V SSTL N29 Bank address bus
K3 DDR3E_CASN 1.5-V SSTL H29 Column address select
K7 DDR3E_CK_N 1.5-V SSTL K25 Clock input N
J7 DDR3E_CK_P 1.5-V SSTL K26 Clock input P
K9 DDR3E_CKE 1.5-V SSTL E30 Clock enable
L2 DDR3E_CSN 1.5-V SSTL H24 Chip select
E3 DDR3E_DQ0 1.5-V SSTL R28 Data bus
F7 DDR3E_DQ1 1.5-V SSTL W28 Data bus
F2 DDR3E_DQ2 1.5-V SSTL V28 Data bus
F8 DDR3E_DQ3 1.5-V SSTL T28 Data bus
H3 DDR3E_DQ4 1.5-V SSTL V30 Data bus
H8 DDR3E_DQ5 1.5-V SSTL Y27 Data bus
G2 DDR3E_DQ6 1.5-V SSTL U29 Data bus
H7 DDR3E_DQ7 1.5-V SSTL Y28 Data bus
D7 DDR3E_DQ8 1.5-V SSTL E32 Data bus
C3 DDR3E_DQ9 1.5-V SSTL D32 Data bus
C8 DDR3E_DQ10 1.5-V SSTL F31 Data bus
C2 DDR3E_DQ11 1.5-V SSTL A32 Data bus
A7 DDR3E_DQ12 1.5-V SSTL B29 Data bus
A2 DDR3E_DQ13 1.5-V SSTL A31 Data bus
B8 DDR3E_DQ14 1.5-V SSTL C30 Data bus
A3 DDR3E_DQ15 1.5-V SSTL D30 Data bus
E3 DDR3E_DQ16 1.5-V SSTL K29 Data bus
F7 DDR3E_DQ17 1.5-V SSTL H31 Data bus
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 8 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description