Measurement Computing CIO-DAS16/330 - Manual (Page 20)

4.12 ENHANCED FEATURES PACER CLOCK DATA & CONTROL REGISTERS
8254 COUNTER 0 DATA - Total Count MS Counter
Chained from counter 1
BASE ADDRESS +16
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
8254 COUNTER 1 DATA - Total Count LS Counter
Clocked by Pacer (See XTAL jumper) - Chained to counter 0
BASE ADDRESS +17
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
8254 COUNTER 2 DATA - Pretrigger Index Counter
BASE ADDRESS +18
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
The three 8254 counter/timer data registers may be written to and read from. Because each counter will count to 65,535,
loading or reading the counter data is a multi-step process. The operation of the 8254 is explained in the section on the
counter/time and the Intel 8254 data sheet.
8254 COUNTER CONTROL
BASE ADDRESS + 19
D1 D2 D3 D4 D5 D6 D7 D8
0 1 2 3 4 5 6 7
This register controls the operation and loading/reading of the counters. The configuration of the 8254 codes which
control the 8254 chip is explained in the Intel 8254 data sheet.
4.13 ANALOG INPUT
Analog signals connected to P3, the 37-pin, D-type connector, are first fed into the two HI-0508 analog multiplexers. A
multiplexer's function is to select one of eight inputs and connect that input to the MUX output. MUX U27 connects
CH0-CH7 high inputs. MUX U28 connects CH0-CH7 Low input (differential input mode) or CH8-CH15 High inputs
(single-ended mode) depending on the state of the channel configuration switch located at the upper right of the board
and marked 8/16.
From the output of the MUX, the analog signal is fed into a programmable differential amplifier.
The A/D converter chip has an integral sample & hold circuit, greatly simplifying design and improving signal integrity.
The A/D converter is capable of sampling rates to 330 kHz.
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