Sensoray 518 - Manual (Page 55)

54
As it turns out, acquisition latency actually takes somewhat longer than the theoretical
maximums discussed here. Additional time is consumed by the host processor itself, either by
polling the 518’s handshake status port or by interrupt overhead in the case of interrupt-driven
host processors.
Processor Speed
Host processor speed is constrained by the bus interface circuitry on the sensor coprocessor
board. The bus interface is designed to work with hosts operating at up to 20 MHz with no wait
states. If you have a faster processor or a heavily loaded backplane, you may need to insert wait
states into your host’s access cycles to ensure reliable operation. Many popular high-speed
processors automatically introduce wait states during I/O operations.
At the other end of the speed spectrum, there is no bottom limit on host processor speed except
for the following: read and write strobes to the 518 must not exceed 5 microseconds in duration.
Communication handshake integrity cannot be guaranteed if host read/write access strobes
exceed 5 microseconds.