Sensoray 626 - Manual (Page 27)

Sensoray Model 626 Instruction Manual 25
11.3 Digital Outputs 0-5 Source Selection
Bits 4-9 of MISC2 (90 hex) are used to select the function of Outputs 0-5.
They can be setup either as standard digital outputs or to pull the output load low for a short pulse when
the corresponding counter overflows.
Before writing to any of the bits of MISC2, except bit 15 (Clear watchdog), the write enable (bit 15) of
MISC1 must be set. This is to prevent accidental modification of the watchdog settings by a crashed
CPU. It is a good idea to clear this bit immediately after writing to MISC2.
MISC2 can not be used to read back the value that bits 4-9 were previously set to. This has to be done
by reading the Counter Register B of each counter as shown below.
Table 23 Reading back Digital Outputs 1-7 Source Selection
Register Bit Digital I/O PIN Function
14 0 0=Digital input, 1= Counter 0A Overflow
CR0B (02 Hex)
13 1 0=Digital input, 1= Counter 0B Overflow
14 2 0=Digital input, 1= Counter 1A Overflow
CR1B (06 Hex)
13 3 0=Digital input, 1= Counter 1B Overflow
14 4 0=Digital input, 1= Counter 2A Overflow
CR2B (0A Hex)
13 5 0=Digital input, 1= Counter 2B Overflow
12. Battery Backup
A 3.6V Nickel Cadmium battery can be connected to the 626 using JP1. Make sure that it is connected
correctly or damage will occur. It will be trickle charged at approximately 100mA if the “Charge
Enable” bit of MISC2 is set.(See “Battery Charging” P23).
While the backup battery is connected & charged the system clock can be made to run during a power
failure to ensure that the counters do not loose counts. To do this the “Battery Enable” bit of Misc2 must
be set to enable the backup battery. In this state the counter setup registers and the count that the counter
were at when the power failed will be held and the counters will continue to count so no counts will be
lost. If a counter interrupt occurs during backup (like a counter overflow) then the appropriate interrupt
register will be set (Counter overflow or index) but the interrupt enable is cleared when the main power
to the system is restored and the system is booted. This is done to allow the user time to initialize
everything. The moment the interrupts are re-enabled, the interrupt will be passed on to the system.