Sundance SMT329 - Manual (Page 36)

4.5.4 IO Control and Status registers
There are 6 IO control and status registers, which control interrupts, comm port channel
switching, VME master cycles, activity indicators, and provide interrupt status.
Individual I/O register addresses are detailed in the following table:
Area VME offset TIM address Title Read/Write
CONTROL E0-E3 C000 0000 Control 1 Read/Write
CONTROL E4-E7 C000 0001 Control 2 Read/Write
CONTROL E8-EB C000 0002 Control 3 Read/Write
CONTROL EC-EF C000 0003 Control 4 Read/Write
CONTROL F0-F3 C000 0004 Status 1 Read
CONTROL F4-F7 C000 0005 Control 6 Read/Write
CONTROL F8-FB C000 0006 Control 7 Read/Write
CONTROL FC-FF C000 0007 Reserved -
4.5.4.1 Control Registers 1 & 2 = TIM Sites 1 & 4 Interrupt Masks
The SMT329 can generate an interrupt to either TIM1 or TIM4 using the signal IIOF1. These
registers provide mask bits to allow software to enable and disable different interrupt
sources.
Control register 1 contains the interrupt masks for TIM 1.
Control register 2 contains the interrupt masks for TIM 4.
Each register has the following bits:
31-16 15-9 8 7-1 0
VME bus error Soft int
R, 0000 0000 R, 0000 000 RW, 0 R, 0000000 RW, 0
VME Bus Error is latched when the VME bus error mask bit for either TIM1 or TIM4 is set.
Therefore both must be cleared to unlatch ‘VME Bus Error’, and at least 1 must be set to latch
‘VME Bus Error’.
The software interrupt (soft int) will always generate an interrupt when it is unmasked.
Note that a TIM must execute an ‘IACK’ instruction to external memory before any TIM
interrupts can be generated. This is usually done by the TIM start up firmware.
User Manual SMT329 Page 36 of 52 Last Edited: 09/02/2007 10:58:00