C.10.2 model 2xx servers – Intel AS/400 RISC Server User Manual
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77800
10950
20200
20200
24
16 MB
600
840-2461 (1548)
77800
10950
16500
20200
24
16 MB
600
840-2461 (1547)
77800
10950
10000
20200
24
16 MB
600
840-2461 (1546)
77800
10950
4550
20200
24
16 MB
600
840-2461 (1545)
MCU
Processor
CIW
Interactive
CPW
Processor
CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.9.1.1 Model 8xx Servers
Note: 830 models were first available in V4R5.
C.10.2 Model 2xx Servers
6660
840
70
2350
2
4 MB
600
270-2434 (1520)
6660
840
0
2350
2
4 MB
600
270-2434 (1516)
3070
380
50
1070
1
2 MB
540
270-2432 (1519)
3070
380
0
1070
1
2 MB
540
270-2432 (1516)
1490
185
30
465
1
n/a
540
270-2431 (1518)
MCU
Processor
CIW
Interactive
CPW
Processor
CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.10.2.1 Model 2xx Servers
C.10.3 V5R1 Dedicated Server for Domino
11810
1670
0
380
4
4 MB
600
820-2458 (none)
6660
840
0
240
2
4 MB
600
820-2457 (none)
3110
385
0
120
1
2 MB
600
820-2456 (none)
6660
840
0
240
2
4 MB
600
270-2454 (none)
3070
380
0
100
1
2 MB
540
270-2452 (none)
MCU
Processor
CIW
Interactive
CPW
NonDomino
CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.10.3 .1 Dedicated Servers for Domino
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
Appendix C CPW, CIW and MCU for System i Platform
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