C.11.2 model 2xx servers, C.11.3 dedicated server for domino – Intel AS/400 RISC Server User Manual
Page 360
16500
16500
24
8 MB
500
840-2420 (1547)
10000
16500
24
8 MB
500
840-2420 (1546)
4550
16500
24
8 MB
500
840-2420 (1545)
2000
16500
24
8 MB
500
840-2420 (1544)
1050
16500
24
8 MB
500
840-2420 (1543)
560
16500
24
8 MB
500
840-2420 (1542)
240
16500
24
8 MB
500
840-2420 (1541)
120
16500
24
8 MB
500
840-2420 (1540)
10000
10000
12
8 MB
500
840-2418 (1546)
4550
10000
12
8 MB
500
840-2418 (1545)
2000
10000
12
8 MB
500
840-2418 (1544)
1050
10000
12
8 MB
500
840-2418 (1543)
560
10000
12
8 MB
500
840-2418 (1542)
240
10000
12
8 MB
500
840-2418 (1541)
120
10000
12
8 MB
500
840-2418 (1540)
4550
7350
8
4 MB
540
830-2403 (1537)
2000
7350
8
4 MB
540
830-2403 (1536)
1050
7350
8
4 MB
540
830-2403 (1535)
560
7350
8
4 MB
540
830-2403 (1534)
240
7350
8
4 MB
540
830-2403 (1533)
120
7350
8
4 MB
540
830-2403 (1532)
70
7350
8
4 MB
540
830-2403 (1531)
2000
4200
4
4 MB
540
830-2402 (1536)
1050
4200
4
4 MB
540
830-2402 (1535)
560
4200
4
4 MB
540
830-2402 (1534)
Interactive CPW
Processor CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
C.11.2 Model 2xx Servers
70
2000
2
4 MB
450
270-2253 (1520)
0
2000
2
4 MB
450
270-2253 (1516)
50
950
1
2 MB
450
270-2252 (1519)
0
950
1
2 MB
450
270-2252 (1516)
30
370
1
n/a
400
270-2250 (1518)
0
370
1
n/a
400
270-2250 (1516)
25
150
1
n/a
400
270-2248 (1517)
20
75
1
n/a
200
250-2296
15
50
1
n/a
200
250-2295
Interactive CPW
Processor CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.11.2.1 Model 2xx Servers
C.11.3 Dedicated Server for Domino
0
200
2
4 MB
450
270-2424
0
100
1
2 MB
450
270-2423
0
50
1
n/a
400
270-2422
0
300
4
4 MB
500
820-2427
0
200
2
4 MB
500
820-2426
0
100
1
2 MB
450
820-2425
Interactive CPW
Non Domino
CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
Table C.11.3.1 Dedicated Server for Domino
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
Appendix C CPW, CIW and MCU for System i Platform
360