C.1 v6r1 additions (october 2008) – Intel AS/400 RISC Server User Manual

Page 345

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C.1 V6R1 Additions (October 2008)

C.1.1 CPW values for the IBM Power Systems

-

IBM i operating system

77600

56800

40300

21600

11000

2x4MB / 32MB

5.0

7388

570 (9117-MMA)

70000

51500

36200

19400

9850

2x4MB / 32MB

4.4

7387

570 (9117-MMA)

16 cores

12 cores

8 cores

4 cores

2 cores

L2/L3 cache

(1)

per chip

Chip Speed

GHz

Processor

Feature

Model

Processor CPW

Table C.1.1. CPW values for Power System Models

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between

two processor cores.

2. Memory speed differences account for some slight variations in performance difference

between models.

3. CPW values for Power System models introduced in October 2008 were based on IBM i 6.1

plus enhancements in post-release PTFs.

C.1.2 CPW values for the IBM Power Systems

-

IBM i operating system

104800

81600

56400

31900

16200

2x4MB / 32MB

4.2

7540

570 (9117-MMA)

32 cores

24 cores

16 cores

8 cores

4 cores

L2/L3 cache

(1)

per chip

Chip Speed

GHz

Processor

Feature

Model

Processor CPW

Table C.1.2. CPW values for Power System Models

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between

two processor cores.

2. Memory speed differences account for some slight variations in performance difference

between models.

3. For large partitions, some workloads may experience nonlinear scaling at high system

utilization on these new models.

4. CPW values for Power System models introduced in October 2008 were based on IBM i 6.1

plus enhancements in post-release PTFs.

C.1.3 CPW values for IBM Power Systems

-

IBM i operating system

48500

27600

14100

2x4MB / 32MB

3.6

7537

560 (8234-EMA)

16 cores

8 cores

4 cores

L2/L3 cache

(1)

per chip

Chip Speed

GHz

Processor

Feature

Model

Processor CPW

Table C.1.3. CPW values for Power System Models

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between

two processor cores.

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

©

Copyright IBM Corp. 2008

Appendix C CPW, CIW and MCU for System i Platform

345

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