VXI SM8000 User Manual

Page 43

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VXI Technology, Inc.

SM8000 Series Programming

43

Trace RAM End High Register – Read and Write

ADDR

Plug-In LA+0x2C

D15-D4

Unused

Data written to these bits have no affect and read back as 1s.

D3-D0

Sets the four most significant bits of the ending address of the
Trace RAM, allowing the available RAM to be divided into
multiple traces.


Trace RAM End Low Register – Read and Write

ADDR

Plug-In LA+0x2E

D15-D0

Sets the 16 least significant bits of the ending address of the Trace
RAM, allowing the available RAM to be divided into multiple
traces.


Trace RAM Address HIGH Register – Read and Write

ADDR

Plug-In LA+0x30

D15-D4

Unused

Data written to these bits have no affect and read back as 1s.

D3-D0

Sets and reads back the four most significant bits of the current
address of the Trace RAM, allowing the current trace RAM
address to be queried and changed.


Trace RAM Address LOW Register – Read and Write

ADDR

Plug-In LA+0x32

D15-D0

Sets and reads back the sixteen least significant bits of the current
address of the Trace RAM, allowing the current trace RAM
address to be queried and changed.


Trace Advance Trigger Select Register – Write Only

ADDR

Plug-In LA+0x34

D15-D8

Sets the TTLTRIG line or lines, which are configured as outputs,
and will toggle when Trace Advance condition occurs in the
module. D15 corresponds to TTLTRIG7, D14 to TTLTRIG6, …
and D8 to TTLTRIG0. Setting a bit to a 1 enables the trigger line,
setting a bit to 0 disables the corresponding line. All bits are set to
0s when either a soft or a hard reset is received by the module.

D7-D0

Sets the TTLTRIG line or lines, which are configured as inputs,
and will cause a Trace Advance event to occur in the module. D7
corresponds to TTLTRIG7, D6 to TTLTRIG6, … and D0 to
TTLTRIG0. Setting a bit to a 1 enables the trigger line, setting a
bit to 0 disables the corresponding line. All enabled TTLTRIG
lines are OR’d together to allow more than one TTLTRIG line to
cause a Trace Advance event to occur. All bits are set to 0s when
the module receives either a soft or a hard reset.

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