Change notification, Figure 4-2. digital filter timing, Change notification -5 – National Instruments DAQ 6527 User Manual

Page 33: Figure 4-2, Digital filter timing -5

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Chapter 4

Device Overview

© National Instruments Corporation

4-5

6527 User Manual

Figure 4-2 shows a filter configuration with an 800 ns filter interval (400 ns
filter clock). In practice, a much slower filter interval is recommended. In
periods A and B the filter blocks the glitches because the external signal
does not remain steadily high from one filter clock to the next. In period C,
the filter passes the transition because the external signal does remain
steadily high. Depending on when the transition occurs, the filter may
require up to two filter clocks—one full filter interval—to pass a transition.
The figure shows a rising 0-to-1 transition; the same filtering applies to
falling 1-to-0 transitions.

Figure 4-2. Digital Filter Timing

Change Notification

You can program the 6527 to notify you of changes on input lines. Change
notification can reduce the number of reads your software must perform to
monitor inputs. Instead of reading the inputs continuously, your software
reacts only to transitions.

You can monitor changes on selected input lines or on all lines. You can
monitor for rising edges (0-to-1), falling edges (1-to-0), or both. When an
input change occurs matching your criteria, the 6527 generates an interrupt.
The NI-DAQ driver can then notify your software using a DAQ event,
message, or LabVIEW occurrence. See your software documentation for
information about support for event notification in your software
environment.

The 6527 notifies you when any one of the changes you are monitoring
occurs; the 6527 does not report which line changed or whether the line
rose or fell. After a change, you can read the input lines to determine the
current line states. The maximum rate of change notification is therefore
limited by software response time and varies from system to system.

External

Signal

External

Signal

Sampled

Filter

Clock

Sample Clock (100 ns)

Filtered

Signal

H

H

H

H

H

H

L

L

H

H

H

L

L

H

H

A

B

C

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