NEC PD78214 - Manual (Page 346)

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Chapter 12 Interrupt Functions
12
Example of correct coding (2)
LOOP: BT IF0H.3, $NEXT
BR $LOOP
NEXT: ←
2. In addition, when you have to use a coding of the instructions listed above consecutively, yet expect frequent occurrence of
interrupts and macro services, insert NOP instructions in the coding to allow time during which interrupts and macro service
can be accepted.
12.3.6 Interrupt and Macro Service Operation Timing
(1) Generation and acceptance of an interrupt request
An interrupt request is generated by hardware. The generated interrupt request sets the corresponding
interrupt request flag to 1.
When the interrupt request flag is set to 1, three clocks (0.5
µs at f
CLK
= 6 MHz) are required to identify the
priority of the interrupt request.
If the acceptance of the interrupt request is allowed when the current instruction has been executed, the
interrupt request is accepted. If the current instruction is one that keeps interrupt requests and macro services
pending, the interrupt request is accepted after the instruction next to that instruction has been executed. (See
Section 12.3.5 for instructions that keep interrupt requests and macro services pending.)
Fig. 12-13 Interrupt Request Generation and Acceptance (Unit: Clock)
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Interrupts or macro services will not be kept pending long,
because they are processed after the BR is executed.
Remark The BTCLR would be more convenient than the
BT, because it clears the flags automatically.
(2) Interrupt request acceptance time
The time listed in Table 12-5 is required to accept each interrupt request. The interrupt handling program
starts running after the time listed in Table 12-5 has elapsed.
Table 12-5 Interrupt Request Acceptance Processing Time Note
Internal ROM fetch
External ROM fetch
Stack area
Program fetch
Internal RAM
18
24 + w × 3
Peripheral RAM
24
30 + w × 3
External memory
24 + w × 3
30 + w × 6
(Unit: Clock)
(w = number of wait cycles)
Note The time listed here does not include the time that elapses before the current instruction is completed or the time required to identify
the priority of the interrupt request.
Remarks 1. The values on the “Internal ROM fetch” row apply when the program is fetched from the internal ROM with IFCH bit of the memory
expansion mode register (MM) set to 1. If the IFCH bit is 0, the same values as when the program is fetched from an external
ROM apply.
2. “Internal RAM” is located at addresses 0FE00H through 0FEFFH.
3 clocks
Instruction Interrupt request accepting processing/macro service processing
Interrupt request flag