Figure 8-27. pulse generation for ets, Counter timing signals, Counter timing signals -25 – National Instruments Data Acquisition Device NI USB-621x User Manual
Page 118
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Chapter 8
Counters
© National Instruments Corporation
8-25
for ETS; the delay from the trigger to the pulse increases after each
subsequent Gate active edge.
Figure 8-27. Pulse Generation for ETS
For information about connecting counter signals, refer to the
section.
Counter Timing Signals
USB-621x devices feature the following counter timing signals:
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•
•
•
•
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Counter n Internal Output Signal
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In this section, n refers to either Counter 0 or 1. For example, Counter n
Source refers to two signals—Counter 0 Source (the source input to
Counter 0) and Counter 1 Source (the source input to Counter 1).
OUT
D1
D2 = D1 +
ΔD D3 = D1 + 2ΔD
GATE
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