Cirrus Logic CS53L21 - Manual (Page 19)

DS700PP1 19
CS53L21
POWER CONSUMPTION
See (Note 17)
17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
18. RESET pin 25 held LO, all clocks and data lines are held LO.
19. RESET pin 25 held HI, all clocks and data lines are held HI.
20. VL current will slightly increase in master mode.
Power Ctl. Registers Typical Current (mA)
Operation
02h 03h
Reserved bit 6 Reserved bit 5 PDN_PGAB PDN_PGAA PDN_ADC
B
PDN_ADC
A
PDN PDN_MICB PDN_MICA PDN_MICBIAS V
i
VA
i
VD
i
VL
(Note 20)
Total
Power
(mW
rms
)
1 Off (Note 18)
x x x x x x x x x x 1.8 0 0 0 0
2.5 0 0 0 0
2 Standby (Note 19)
x x x x x x 1 x x x 1.8 0.01 0.02 0 0.05
2.5 0.01 0.03 0 0.10
3 Mono Record ADC 1 1 1 1 1 0 0 1 1 1 1.8 1.85 2.03 0.03 7.05
2.5 2.07 3.05 0.05 12.94
PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8 2.35 2.03 0.03 7.95
2.5 2.58 3.08 0.05 14.29
MIC to PGA to ADC
(with Bias)
1 1 1 0 1 0 0 1 0 0 1.8 3.67 2.05 0.03 10.36
2.5 3.95 3.09 0.05 17.71
MIC to PGA to ADC
(no Bias)
1 1 1 0 1 0 0 1 0 1 1.8 3.27 2.03 0.03 9.61
2.5 3.52 3.08 0.05 16.62
4 Stereo Record ADC 1 1 1 1 0 0 0 1 1 1 1.8 2.69 2.12 0.03 8.72
2.5 2.93 3.18 0.04 15.40
PGA to ADC 1 1 0 0 0 0 0 1 1 1 1.8 3.65 2.12 0.03 10.45
2.5 3.91 3.17 0.04 17.84
MIC to PGA to ADC
(no Bias)
1 1 0 0 0 0 0 0 0 1 1.8 5.48 2.11 0.03 13.73
2.5 5.76 3.17 0.04 22.45