ADLINK PCIe-7350 - Manual (Page 35)

Function Block and Operation Theory 25
Figure 3-3: DI Row Data Mapping for 16 Bits Data Width
CH15 ~ CH0
(sample #1)
CH7 ~ CH0 CH23 ~ CH16
Configured
input ports
A B C D
A B C D
A B C D
A B C D
Configured
input ports
Configured
input ports
Configured
input ports
CH15 ~ CH0
(sample #2)
CH23 ~ CH8
(sample #1)
CH23 ~ CH8
(sample #2)
A B C D
Configured
input ports
(sample #1)
CH7 ~ CH0 CH23 ~ CH16
(sample #2)
CH7 ~ CH0 CH31 ~ CH24
(sample #1)
CH7 ~ CH0 CH31 ~ CH24
(sample #2)
CH15 ~ CH8 CH31 ~ CH24
(sample #1)
CH15 ~ CH8 CH31 ~ CH24
(sample #2)
A B C D
Configured
input ports
CH31 ~ CH16
(sample #1)
CH31 ~ CH16
(sample #2)