ADLINK PCIe-7350 - Manual (Page 71)

Function Block and Operation Theory 61
I
2
C master of PCIe-7350 supports the clock range from 1.9 kHz to
244.14 kHz. After issuing command to I
2
C slave device, the clock
rate might be changed according the request from I
2
C slave. The
below formula is to calculate the I
2
C clock rate.
F
scl
= 488.28 / (Clk Pre-scale + 1) (kHz), 
where Clk Pre-scale = 1~255
I
2
C Write Command:
the content of Cmd/Addr and Data are
stored in registers I
2
C_A_CA and I
2
C_A_DAT and their byte
counts are indicated by I
2
C CmdAddr Byte Count and Access Byte
Count, respectively.
I
2
C Read Command:
the format of Read command is similar with
a write command except that the data part is derived by slave
device.
I
2
C Cmd/Addr Count is less than 4 byte:
I
2
C Data Count is less than 4 byte:
Figure 3-30: I
2
C Data Format
S P
W
Slave Addr
A
C
K
n
A
C
K
Cmd/Addr
0 ~ 4 Bytes
A
C
K
Data to Slave
0 ~ 4 Bytes
S P
R
Slave Addr
A
C
K
n
A
C
K
Cmd/Addr
0 ~ 4 Bytes
A
C
K
Data from Slave
0 ~ 4 Bytes
S P
W
Slave Addr
A
C
K
n
A
C
K
Cmd/Addr #0
A
C
K
Data to Slave
0 ~ 4 Bytes
A
C
K
Cmd/Addr two bytes ( I2C CmdAddr Byte Count = 2 )
Cmd/Addr #1
S P
W
Slave Addr
A
C
K
n
A
C
K
A
C
K A
C
K
Data two bytes ( I2C Data Byte Count = 2 )
Data #0
Cmd/Addr
0 ~ 4 Bytes
Data #1