Reset sequence, Reset sequence -25 – Altera JESD204B IP User Manual
Page 62
Reset Signal
Associated Clock
Description
tx_analogreset[L-1:0]
rx_analogreset[L-1:0]
Transceiver Native PHY
Analog Reset
Active high reset controlled by the transceiver
reset controller. This signal resets the TX/RX
PMA.
The link clock, frame clock, and AVS clock
reset signals (
txlink_rst_n
/
rxlink_rst_n
,
txframe_rst_n
/
rxframe_rst_n
and
jesd204_tx_avs_rst_n
/
jesd204_rx_avs_
rst_n
) can only be deasserted after the
transceiver comes out of reset.
(21)
tx_digitalreset[L-1:0]
rx_digitalreset[L-1:0]
Transceiver Native PHY
Digital Reset
Active high reset controlled by the transceiver
reset controller. This signal resets the TX/RX
PCS.
The link clock, frame clock, and AVS clock
reset signals (
txlink_rst_n
/
rxlink_rst_n
,
txframe_rst_n
/
rxframe_rst_n
and
jesd204_tx_avs_rst_n
/
jesd204_rx_avs_
rst_n
) can only be deasserted after the
transceiver comes out of reset.
(21)
jesd204_tx_avs_rst_n
jesd204_rx_avs_rst_n
TX/RX AVS (CSR)
Clock
Active low reset controlled by the clock and
reset unit. Typically, both signals can be
deasserted after the core PLL and transceiver
PLL are locked and out of reset. If you want to
dynamically modify the LMF at run-time, you
can program the CSRs after AVS reset is
deasserted. This phase is referred to as the
configuration phase.
After the configuration phase is complete, then
only the
txlink_rst_n
/
rxlink_rst_n
and
txframe_rst_n
/
rxframe_rst_n
signals can be
deasserted.
Related Information
•
•
Reset Sequence
Altera recommends that you assert reset for the JESD204B IP core and transport layer when powering up
the PLLs and transceiver.
(21)
Refer to the Altera Transceiver PHY IP Core User Guide and Altera Arria 10 Transceiver PHY IP Core
User Guide for the timing diagram of the
tx_analogreset
,
rx_analogreset
,
tx_digitalreset
, and
rx_digitalreset
signals.
UG-01142
2015.05.04
Reset Sequence
4-25
JESD204B IP Core Functional Description
Altera Corporation