Tx path – Altera JESD204B IP User Manual
Page 91
Figure 5-2: Mapping of Data Bit and Content Across Various Interfaces (LMF = 112, N = 12, N' = 16, S =
1, T represents the tail bits).
0
1
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11
[0]
[0]
[1]
[2]
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[11]
[0]
[1]
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T
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31
2nd jesd204_tx_datain[11:0]
(Avalon-ST interface to Transport Layer)
2nd jesd204_tx_ctrlin[0]
(Avalon-ST interface to Transport Layer)
[0]
[0]
[0]
[0]
[0]
1st jesd204_tx_ctrlin[0]
(Avalon-ST interface to Transport Layer)
[0]
1st jesd204_rx_ctrlout[0]
(Transport Layer to Avalon-ST Interface)
[0]
2nd jesd204_rx_ctrlout[0]
(Transport Layer to Avalon-ST Interface)
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
2nd jesd204_rx_dataout[11:0]
(Transport Layer to Avalon-ST Interface)
1st jesd204_tx_datain[11:0]
(Avalon-ST interface to Transport Layer)
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
1st jesd204_rx_dataout[11:0]
(Transport Layer to Avalon-ST Interface)
Bit Position
TX to RX Channel
jesd204_tx_link_datain[31:0]
(Transport Layer to Data Link Layer)
[0]
[1]
[2]
[3]
[4]
[5]
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[8]
[9]
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[11]
[0]
[1]
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[11]
T
T
T
T
T
T
jesd204_rx_link_datain[31:0]
(Data Link Layer to Transport Layer)
TX Path
The assembler in the TX path consists of the tail bits dropping, assembling, and multiplexing blocks.
5-10
TX Path
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines