Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 89)

VHDL Master BFM
Master Assertions
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 89
April 2014
1.
Refer to Master Timing and Events for details of simulator time-steps.
Master Assertions
The master BFM performs protocol error checking via built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
By default, all built-in assertions are enabled in the master BFM. To globally disable them in the
master BFM, use the
set_config() command as shown in Example 8-1 .
Example 8-1. Master BFM Disable All Assertions
set_config(AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS, 0, bfm_index,
axi4stream_tr_if_0(bfm_index));
AXI4STREAM_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay permitted
between individual transfers in
clock cycles. Default: 10000.
AXI4STREAM_CONFIG_MAX_LATENCY_TVALID_
ASSERTION_TO_TREADY The maximum delay permitted
between the assertion of TVALID
to the assertion of TREADY.
Default: 10000.
Master Attributes
AXI4STREAM_LAST_DURING_IDLE Controls the value of TLAST
during idle.
0 = TLAST driven to 0 during
idle (default)
1 = TLAST driven to 1 during
idle
Error Detection
AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all
assertion checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4STREAM_CONFIG_ENABLE_ASSERTION Individual enable/disable of an
assertion check in the BFM. Refer
to the
Master Assertions chapter
for details.
0 = disabled
1 = enabled (default)
Table 8-2. Master BFM Configuration (cont.)
Configuration Field Description