Zilog Z86193 - Manual (Page 190)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
183
Increment
Instruction Format
Operation
dst
←
dst + 1
The contents of the destination operand are incremented by one.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
destination Working Register operand is specified by adding
1110b
(
Eh
) to the high nibble
of the operand. For example, if Working Register R12 (CH) is the destination operand, then
ECh
is used as the destination operand in the Op Code.
Example 1
If Working Register R10 contains
2Ah
, the statement:
INC R10
Op Code: AE
leaves the value 2Bh in Working Register R10. The Z, V, and S Flags are cleared.
Example 2
If Register
B3h
contains
CBh
, the statement:
INC B3h
Op Code: 20 B3
leaves the value
CCh
in Register
CBh
. The S Flag is set, and the Z and V Flags are cleared.
Cycles
OPC
(Hex)
Address Mode
dst
dst OPC 6 rE r
OPC dst
6 20 R
6 21 IR
Flag Description
C Unaffected
Z Set if the result is zero; cleared otherwise.
S Set if the result of bit 7 is set (negative); cleared otherwise.
V Set if arithmetic overflow occurs; cleared otherwise.
D Unaffected
H Unaffected
E dst
Note: