Figure 4, System timing & control stc – Measurement Computing PCI-DAS6023 User Manual
Page 20
PCI-DAS6023 and PCI-DAS6025 User's Guide
Functional Details
20
Use the SYNC CLCK signal to determine the master/slave configuration of a DAQ-Sync-enabled system. Each
system can have one master and up to three slaves. SYNC CLK is the 40 MHz time base used to derive all
board timing and control. The master provides this clock to the slave boards so that all boards in the DAQ-sync-
enabled system are timed from the same clock.
MEMORY BUS
12-Bit
ADC
Mux
&
Gain
Analog In
16 CH S-E or
8 CH DIFF.
D Q
EOC
12
Holding
Register
40 MHz
A/D PACER OUT
SCANCLK
D/A PACER OUT
A/D CONVERT
A/D START TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
LOCAL BUS
PCI BUS (5V, 32-BIT, 33 MHZ)
Boot
EEPROM
EXT CTR1 CLK
CTR1 CLK
USER
COUNTER
2
Control
82C54
FIRSTPORTA
FIRSTPORTCH
Control
24 Bits DIO
PCI-DAS6025 Only
82C55
USER
COUNTER
1
CTR2 GATE
CTR1 GATE
CTR2 OUT
CTR1 OUT
DIO
8 BITS
DAC0
DAC1
(PCI-DAS6025 Only
12 BITS
12 BITS
DAC
Buffer
(16K)
Queue
Buffer
(8K)
ADC
Buffer
(8K)
10
0-
Pi
n
I/O
C
O
N
N
EC
TO
R
SYSTEM
TIMING
&
CONTROL
STC
FIRSTPORTCL
DIO(7:
0)
FIRSTPORTA (7:
0)
FIRSTPORTB (7:
0)
FIRSTPORTCH (7:
0)
FIRSTPORTCL (7:
0)
Figure 4. Block diagram – PCI-DAS6025 and PCI-DAS6023