Intel PXA255 User Manual
Page 216
6-34
Intel® PXA255 Processor Developer’s Manual
Memory Controller
20:18
SXCL2
CAS Latency for SX Memory partition pair 2/3
Number of external SDCLK cycles between receiving the READ command and latching the
data. The unit size for SXCL2 is the external SDCLK cycle. When SX Memory runs at half
the memory clock frequency (MDREFR:K0DB2 = 1), the delay is 2*memclk. When in doubt
as to which CAS Latency to use, use the next larger.
IF SXTP2 = 00”(SMROM):
000 – reserved
001 – reserved
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – reserved
111 – reserved
IF SXTP2 = 10 (non-SDRAM timing Fast Flash)
000 – reserved
001 – reserved
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – 7 clocks
111 – reserved
17:16
SXEN2
Enable Bits for SX Memory Partition 2 (bit 16) and Partition 3 (bit 17)
0 – Partition is not Enabled as SX Memory
1 – Partition is Enabled as SX Memory
15
—
reserved
14
SXLATCH0
SXMEM latching scheme for pair 0/1
0 – Latch return data with fixed delay on MEMCLK
1 – Latch return data with return clock
Must always be written with a 1 to enable the return clock SDCLK for latching data. For
more detail on this return data latching, see
13:12
SXTP0
SX Memory type for partition pair 0/1
00 – Synchronous Mask ROM (SMROM)
01 – reserved
10 – non-SDRAM-like Synchronous Flash
11 – reserved
Table 6-13. SXCNFG Bit Definitions (Sheet 2 of 4)
0x4800_001C
SXCNFG
Memory Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
re
s
e
rv
e
d
S
X
LA
TC
H
2
SXTP
2
SX
C
A
2
SX
R
A
2
SXRL2
SXCL2
S
XEN
2
re
s
e
rv
e
d
S
X
LA
TC
H
0
SXTP
0
SX
C
A
0
SX
R
A
0
SXRL0
SXCL0
S
XEN
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
Bits
Name
Description