Intel PXA255 - Manual (Page 429)

Intel® PXA255 Processor Developer’s Manual 12-27
USB Device Controller
12.6.3.8 Setup Active (SA)
The Setup Active bit indicates that the current packet in the FIFO is part of a USB setup command.
This bit generates an interrupt and becomes active at the same time as UDCCS0[OPR]. Software
must clear this bit by writing a 1 to it. Both UDCS0[OPR] and UDCCS0[SA] must be cleared.
12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)
UDCCS1/6/11, shown in Table 12-15 , contains 6 bits that are used to operate endpoint(x), a Bulk
IN endpoint).
12.6.4.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is active if one or fewer data packets remain in the transmit FIFO.
TFS is cleared when two complete packets of data remain in the FIFO. A complete packet of data is
signified by loading 64 bytes of data or by setting UDCCSx[TSP].
Table 12-15. UDCCS1/6/11 Bit Definitions
0x 4060_0014
0x 4060_0028
0x 4060_003C
UDCCS1
UDCCS6
UDCCS11
USB Device Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TSP
re
ser
ved
FST SST TU
R
FTF TPC TFS
X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1
Bit Name Description
31:8 — reserved
7 TSP
Transmit short packet
1 = Short packet ready for transmission.
6 — reserved
5 FST
Force STALL
1 = Issue STALL handshakes to IN tokens.
4 SST
Sent STALL
1 = STALL handshake was sent.
3 TUR
Transmit FIFO underrun
1 = Transmit FIFO experienced an underrun.
2 FTF
Flush Tx FIFO
1 = Flush Contents of TX FIFO
1 TPC
Transmit packet complete
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0 TFS
Transmit FIFO service
0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet