Intel PXA255 - Manual (Page 546)

16-4 Intel® PXA255 Processor Developer’s Manual
Network SSP Serial Port
• SSPSCLK–Defines the bit rate at which serial data is driven onto and sampled from the port.
• SSPSFRM–Defines the boundaries of a basic data unit, comprised of multiple serial bits.
• SSPTXD–The serial data path for transmitted data, from system to peripheral.
• SSPRXD–The serial data path for received data, from peripheral to system.
A data frame can contain from four to 32-bits, depending on the selected protocol. Serial data is
transmitted most significant bit first. Four protocols are supported: TI Synchronous Serial
Protocol*, SPI, Microwire*, and a PSP.
The SSPSFRM function and use varies between each protocol.
• For the TI Synchronous Serial Protocol*, SSPSFRM is pulsed high for one (serial) data period
at the start of each frame. Master and slave modes are supported. TI Synchronous Serial
Protocol* is a full-duplex protocol.
• For the SPI* protocol, SSPSFRM functions as a chip select to enable the external device
(target of the transfer) and is held active-low during the data transfer (during continuous
transfers, the SSPSFRM signal is held low). Master and slave modes are supported. SPI* is a
full-duplex protocol.
• For the Microwire* protocol, SSPSFRM functions as a chip select to enable the external
device (target of the transfer) and is held active-low during the data transfer. Slave mode is not
supported for Microwire*. SSPSFRM for Microwire* is also held low during continuous
transfers. Microwire* is a half-duplex protocol.
• For the PSP, SSPSFRM is programmable in direction, delay, polarity, and width. Master and
slave modes are supported. PSP can be programmed to be either full or half duplex.
The SSPSCLK function and use varies between each protocol.
• For TI Synchronous Serial Protocol*, data sources switch transmit data on the rising edge of
SSPSCLK and sample receive data on the falling edge. Master and slave modes are supported.
• For SPI*, the SSP lets programmers select which edge of SSPSCLK to use for switching
transmit data and for sampling receive data. In addition, users can move the phase of
SSPSCLK, shifting its active state one-half cycle earlier or later at the start and end of a frame.
Master and slave modes are supported.
• For Microwire*, both data sources switch (change to the next bit) transmit data on the falling
edge of SSPSCLK and sample receive data on the rising edge. Slave mode is not supported for
Microwire*.
• For PSP, the protocol allows for the configuration of which edge of the SSPSCLK is used for
switching transmit data and the edge for sampling receive data. In addition, the idle state for
SSPSCLK can be controlled and the number of active clocks that precede and follow the data
transmission. Master and slave modes are supported.
Microwire* uses a half-duplex, master-slave messaging protocol. At the start of a frame, the
controller transmits a one or two-byte control message to the peripheral; no data is sent by the
peripheral. The peripheral interprets the message and if the message is a read request, the
peripheral responds with the requested data, one clock after the last bit of the request message.
Return data—part of the same frame—can be from four to 16-bits in length. The total frame length
is 13 to 33 bits. The SSPSCLK is active during the entire frame.
Note: The serial clock (SSPSCLK), if driven by the SSP, toggles only while an active data transfer is
underway, unless receive-without-transmit mode is enabled by setting SSCR1[RWOT] and the
frame format is not Microwire*, in which case the SSPSCLK toggles regardless of whether