6711 cpu overview – Vodafone SS 08 User Manual
Page 19
Advertising
TU Dresden, 4/29/2008
Slide 19
chair
‘6711 CPU Overview
VelociTI Î advanced very-long instruction words (VLIW)
Program Memory Width is 256 Bit
Up to 8 32-Bit instructions can be executed in parallel/Cycle
16, 32 and 40 bit fixed point operands
32 and 64 bit floating point operands
Instruction parallelism is detected at compile-time
no data dependency checking is done in Hardware.
Instruction Packing Reduces Code Size
All operations work on registers
Memory Architecture
4K-Byte L1P Program Cache (Direct Mapped)
4K-Byte L1D Data Cache (2-Way Set-Associative)
64K-Byte L2 Unified Mapped RAM/L2 Cache (Flexible Data/Program
Allocation)
Advertising