Vodafone SS 08 - Manual (Page 24)

TU Dresden, 4/29/2008 Slide 24
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'C6x System Block Diagram
Internal Buses Internal Buses
CPU CPU
.D1 .D1
.M1 .M1
.L1 .L1
.S1 .S1
.D2 .D2
.M2 .M2
.L2 .L2
.S2 .S2
Regs (B0 Regs (B0
- -
B15) B15)
Regs (A0 Regs (A0
- -
A1
5) A1
5)
Control Regs Control Regs
EMIF EMIF
Ext Ext ’ ’ l l
Memory Memory
- - Sync Sync
- - Async Async
Program Program
RAM RAM
Data Ram Data Ram
D (32) D (32)
Serial Port Serial Port
Host Port Host Port
Boot Load Boot Load
Timers Timers
Pwr Down Pwr Down
DMA DMA
Addr Addr