Asus A8V-E SE - Manual (Page 65)

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DRAM Configuration DRAM Configuration DRAM Configuration DRAM Configuration DRAM Configuration
The items in this sub-menu show the DRAM-related information
auto-detected by the BIOS.
F1:Help
↑↓
: Select Item -/+: Change Value F5: Setup Defaults
ESC: Exit
→←
: Select Menu Enter: Select Sub-menu F10: Save and Exit
Select Menu
Item Specific Help
Place an artificial
memory clock limit on
the system. Memory is
prevented from
running faster than
this frequency.
DRAM Configuration
Current DRAM Frequency 200 MHz
Timing Mode [ Auto ]
x Memclock index value (MHz) 200Mhz
x CAS# latency (Tcl) 2.5
x Min RAS# active time(Tras) 8T
x RAS# to CAS# delay (Trcd) 4T
x Row precharge Time (Trp) 4T
x 1T/2T Memory Timing 2T
H/W DRAM Over 4G Remapping [Enabled]
MTRR mapping mode [Continous]
Master ECC Enabled [Enabled]
ECC Memory Interlock [At least One]
Phoenix-Award BIOS CMOS Setup Utility
Advanced
Current DRAM Frequency
Shows the Transfer mode. This item is not configurable.
Timing Mode [Auto]
Sets the timing mode. Configuration options: [Auto] [Manual]
Memclock index value (Mhz) [200Mhz]
Sets the memory clock index value. Configuration options: [100Mhz]
[133Mhz] [166Mhz] [200Mhz] [216Mhz] [233Mhz] [250Mhz]
CAS# latency (Tcl) [2.5]
Controls the latency between the SDRAM read command and the time
the data actually becomes available. Configuration options: [2.0] [2.5]
[3.0]
Min RAS# active time (Tras) [8T]
Sets the minimum RAS# active time. Configuration options: [5] [6]
[7] [8] [9] [10] [11] [12] [13] [14] [15]
RAS# to CAS# delay (Trcd) [4T]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2] [3] [4] [5] [6]
[7]