Motorola MVME1X7P User Manual
Page 279
Programming Model
http://www.motorola.com/computer/literature
4-31
4
The states of RSIZ2-0 after reset (power-up, soft, or local)
match those of the RSIZ2-0 bits from the reset serial bit
stream.
SELI1, SELI0
The SELI1, SELI0 control bits determine the base address
at which the control and status registers respond, as shown
below:
SELI1 and SELI0 are initialized by hardware after a
power-up, soft, or local reset. Their initialized state is
determined by board-level configuration resistors.
FSTRD
The FSTRD control bit determines the speed at which
SDRAM reads occur. When it is 1, SDRAM reads happen
at full speed. When it is 0, SDRAM reads are slowed by
one clock, unless they are already slowed by NCEBEN
RSIZ2
RSIZ1
RSIZ0
DRAM Array Size
0
0
0
4MB
0
0
1
8MB
0
1
0
16MB
0
1
1
32MB
1
0
0
64MB
1
0
1
128MB
1
1
0
Reserved
1
1
1
Reserved
SELI1
SELI0
Register Base Address
0
1
$FFF43000
1
0
$FFF43100